With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Nevertheless, performance improvement brought up by this type of “classic” scaling, in device dimensions, may cause increases in both external resistance and parasitic capacitance. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a thickness of about 30 nm to 100 nm, are generally required for acceptable performance in short channel devices. Semiconductor-on-insulator (SOI) technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In a SOI substrate, a buried oxide (BOX) film comprising silicon dioxide may be formed on a silicon substrate and a single crystal silicon thin film is formed thereon. Various methods of fabricating such SOI substrates are known, one of which is Separation-by-Implanted Oxygen (SIMOX), wherein oxygen is ion implanted into a single crystal silicon substrate to form a BOX film. Another method of forming an SOI substrate is wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates.
The thickness of the silicon layer of an extremely thin silicon on insulator (ETSOI) layer typically ranges from 3 nm to 10 nm. ETSOI technology provides an extremely thin silicon channel wherein the majority carriers are fully depleted during operation.
Scaling of fully depleted CMOS technology, particularly thin SOI devices, requires raised source/drain (S/D) to lower the external resistance. Conventional raised S/D comes with the drawback of increased parasitic capacitance between the raised S/D and the gate. Furthermore, in some device structures, for example, extremely thin SOI (ETSOI), the extension resistance becomes the dominant component of total external resistance. The extension resistance can be lowered by thickening the SOI in extension regions. However, a trade-off is made between two competing requirements—lowering external resistance and minimizing the increase of parasitic capacitance.
The shrinking of device dimensions to 25 nm node and beyond, e.g. 22 nm node, causes an increase in both external resistance and parasitic capacitance. Raised source/drain (RSD) fabrication by epitaxy has been adopted to reduce S/D resistance. Two types of raised RSD devices include vertical RSD and faceted RSD. At a given gate pitch, vertical RSD has enabled the use of a thin spacer and thus increased silicide-to-SD contact area. It therefore advantageously lowers contact resistance. A drawback of this configuration is high parasitic gate-to-SD capacitance.
Faceted RSD devices offer the advantage of reduced gate-to-SD parasitic capacitance, but require a silicide spacer that prevents fully siliciding the thin SOI layer. The relatively thick spacer reduces silicide-to-SD contact area and thus adversely increases contact resistance.
FIG. 9 shows an example of a vertical RSD structure 20. The structure includes a semiconductor on insulator (SOI) substrate including a first semiconductor layer 22, an insulator layer 24, and a second semiconductor layer 26. The first semiconductor layer 22 is an ETSOI layer having a thickness of less than 10 nm, e.g. 6 nm. In this example, the insulator layer 24 is a buried oxide (BOX) layer. A high-k/metal gate structure 28 is formed on the ETSOI layer. RSD regions 30 adjoin the ETSOI channel region. Silicide contact layers 32 are formed on the RSD regions.
FIG. 10 shows a faceted RSD structure 36 having some of the same elements found in the vertical RSD structure 20. In situ boron doped (ISBD) and in situ phosphorus doped (ISPD) faceted epitaxy may, for example, be used to form the RSD regions 38. A second silicide spacer 40 comprising, for example, silicon nitride, is required in this structure 36. High resistivity of the structure 36 is due to reduced silicide-to-SD contact area. A nitride cap may be provided on the gate electrode.